1. Field of the Invention
The present invention relates to an integrated circuit formed on a surface of a semiconductor substrate or another substrate, and to a method for manufacturing same; and particularly relates to structures of a wiring layer and an interlayer insulation film laminated thereon.
2. Description of the Related Art
Circuit elements such as transistors, resistors, and capacitors are formed in semiconductor devices in which circuits are integrated on a semiconductor substrate (integrated circuits) using an impurity diffusion region formed on the semiconductor substrate, polysilicon laminated on the substrates, or the like. A metal film is additionally formed as a wiring layer above the circuit elements with an insulation layer interposed therebetween. By patterning the metal film, wirings for establishing connections including connections between circuit elements, and other components are formed.
In designing a wiring pattern, a plurality of wirings is disposed with a minimum amount of space between the wirings in order to, e.g., increase the degree of integration. FIG. 6 is a plan view showing an example of a conventional pattern of a plurality of wirings having portions that are in proximity to each other. Each of two wirings 2 shown in FIG. 6 change direction therealong by 90°. Horizontal portions 2h of the wirings 2 are disposed parallel to and in proximity to each other. Conversely, vertical parts 2v of each of the wirings 2 are disposed across a large amount of space due, e.g., to each of the wirings 2 having a different connection point. The wiring layer is formed, e.g., by vapor-depositing aluminum (Al).
FIG. 7 is a plan view showing another example of a conventional pattern of a plurality of wirings having proximal portions. Two wirings 4a, 4b shown in FIG. 7 are disposed parallel to and in proximity to each other. At an unspecified point along one of the wirings 4a, the other wiring 4b connects via a contact 6 to a diffusion layer of the semiconductor substrate (not shown) or to lower layer wiring (not shown), and terminates.
Once the wiring layer has been completely patterned, there is formed an interlayer insulation film or a passivation film (collectively termed interlayer insulation films in the present application) for covering the wiring layer. For example, tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), or a silicon nitride film (SiN) is built up using chemical vapor deposition (CVD) or another appropriate method; and an interlayer insulation film is formed. After the interlayer insulation film is built up, a heat treatment can be performed in order to, e.g., planarize the film using a reflow process.
It is possible to laminate another wiring layer on the interlayer insulation film and form wirings, forming a multiple wiring layer structure.